“There is a RISC-V multicore frenzy,” says Frank Schirrmeister, vice president of marketing at Arteris IP. Many questions get raised as soon as multicore enters the picture. While there are a handful of tools that can do some of those tasks, there is nothing that can do them all, and there are no flows that combine multiple tools to accomplish the task. There’s also gaps in tools that can analyze dataflow within the system. There is a dearth of tools that can help partition software, or optimize a processor while considering the memory subsystem or the communications network. With the breadth of options available and the necessary ecosystem to support them, the rate of adoption has been rapid.īut as soon as a design includes multiple processors, or heterogeneous compute environments, the tooling becomes a lot less available. While companies such as Cadence and Synopsys have had internal tools for their proprietary architectures for decades, RISC-V has created a new and open marketplace for such tools. Over the past few years, many tools have emerged that help with the definition and implementation of a single processor, optimized for a given set of software. The design, implementation, and programming of multicore heterogeneous systems is becoming more common, often driven by the software workloads, but the tooling to help optimize the processors, interconnect, and memory are disjointed.
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